Turning to FIG. 1A-1B, disclosed are various prior art digital potentiometer (DP) ladders. DP ladders can be used in digital to analog converters.
In FIG. 1A, a DP ladder 100 is disclosed. In the DP ladder 100, there are a plurality of resistors, each one with a substantially equal value. Therefore, the voltage output at node “W” is determined in a linear manner as determined by which one of switches 101-108 are closed. A disadvantage of the DP ladder 100 is that a corresponding switch is needed for each graduated voltage level, and therefore the DP ladder 100 has substantial implementation drawbacks. One reason for these drawbacks is that implementing these switches is not practical for a DP is because the “variable resistance” function of a DP requires that these switches be very low ohmic, or very large (i.e. more area, more cost).
FIG. 1B is directed to one aspect of a DP ladder 160, as disclosed in “Resistor String Digital-to-Analog Converter”, U.S. Pat. No. 5,808,576 to Chloupek, et al. FIG. 1B employs a top array of resistors RTOP and a bottom array off resistors RBOT, wherein a sum of the first variable resistance of the RTOP and the second variable resistance of RBOT is a fixed resistance value. This approach is also advantageous over FIG. 1A, in that the number of switches needed to convey an analog value is greatly reduced when compared to the DP ladder 100.
However, although the DP ladder 160 has significant advantages when compared to the DP ladder 100, it also has certain significant disadvantages as well.
A glitch can be generally defined as an unwanted/undesired analog signal spike, be it voltage, current, etc., that exceeds a selected criteria. A common problem encountered in multiple string architectures, such as that of a DP ladder, is the presence of a large undesired transient (a “glitch”) in the transient response during a certain code-to code transitions. Code-to-code transitions can be generally defined as a change of a first digital value to a second digital value to be output as an analog signal. Undesired output transients, i.e. “glitches”, such as can occur with the DP ladder 160.
Aside from impacting the signal integrity of the output, this undesired transient can have serious implications at the system level where an entire system can be overdriven, leading to possible breakdown and/or settling time issues. Improvement in this undesired transient has variously been addressed either by reducing the sources that contribute to the undesired transient and/or dampening the undesired transient with a large capacitor.
Reduction of the undesired transient contributors typically has a lower practical limit due to such factors as large coupling parasitics present in a digital to analog converter (DAC), such as a digital potentiometer. This is further complicated by the fact that each transition relies on precise simultaneous switching of different strings.
Most of the approaches targeting purported sources of the undesired output transient in DP ladders tend to be implemented at the switch level, for example, adding dummy switches, slowing the switch ramp rate, staggering the switching of the individual fingers, etc. Disadvantageously, these techniques typically slow down the settling time of the transient, and tend to require a larger area overhead as the number of switches in the DAC/digital potentiometer increases.
Capacitors have been used to dampen an undesired transient have been used in the prior art. However, capacitors, especially large capacitors, can also significantly increase the transient settling time, and furthermore typically degrades the operation of the digital potentiometer in terms of frequency throughput.
Generally, one possibility to avoid output undesired transients on an analog output is to dynamically switch an output capacitor in and out when needed. As the digital potentiometer (or other analog output device) has a high impedance output node for the analog signal, the capacitor therefore should to be pre-charged to be equal to an output voltage before being connected to the output. However, this approach requires additional overhead both in area and power for the pre-charging circuitry.
FIG. 2 illustrates an alternative aspect of a DP ladder, a prior art “sliding scale” DP ladder 201. In the DP ladder 201, a coarse string is segmented based upon the upper most significant bits (MSBs), and a fine string is segmented based upon the least significant bits (LSBs).
An advantage of the DP ladder 201 over the DP ladder 100 is that the number of switches needed to represent an analog value is greatly reduced, for example from 128 switches to 32 switches, wherein the number 128 is derived from an example of a 7-bit DP. The number of switches can depend upon the segmentation of the coarse/fine strings. If the coarse string was the upper 4 MSB bits, you would have 24=16 switches (each switch represents 1 code) at the DP ladder. This means that the fine string has 23=8 switches, and since two fine strings are employed, the total switch count is 24+2*23=32 switches compared to 128. Another advantage is that larger resistances can be used in the DP ladder 130, which is advantageous in terms of accuracy and precision of manufacturing processes.
Generally speaking, a goal of a code-to-code transition in the DP is to change the DP ladder 201 by a single LSB unit. For a typical transition, what happens is that the two LSB strings 220 and 225 both change by one LSB. This causes both ends of the MSB string to “slide” up (or down) by one LSB. Since this is a passive string, all the intermediate nodes in the MSB string will also “slide” by one LSB and the desired change is obtained at the output.
For example, at code 0, the switches that are turned on are 226, 221, and 253. For a transition to code 1, the switches will change to 227, 222, and 253 (note that the MSB switch doesn't change). A problematic transition is when the transition involves changing a switch in MSB string 250. For this example, this would be from code 2 (228, 223, and 253) to code 3 (226, 221, and 252).
What happens here is that both the LSB strings 220 and 225 are making a change of −(1 MSB−1 LSB). Again, both sides of the MSB string 250 see the −(1 MSB−1 LSB) change and so all the intermediate nodes (i.e. the one connected to switch 252) also see this −(1 MSB−1 LSB) change. At this same instance, changing from 253 to 252 results in a +1 MSB change at the wiper terminal. By superposition, the net change is the sum of these two changes [+1 MSB−(1 MSB−1 LSB)]=+1 LSB and so the desired change is obtained at the output. The problem is that these two changes should occur at the same exact instance.
For example, if the +1 MSB changes first, then a glitch of +1 MSB occurs before and vice versa if the −(1 MSB−1 LSB) changed first, changes of switches 221-223 and 226-228 the LSB strings 220, 225, without a MSB change 250, generally does not lead to significant undesired transient (glitch), “significant” generally defined as, such as glitch comparable to the size of 1 LSB unit. However, a transition of a switch 251-253 of MSB 250, especially with a change of the switch of the LSB string 220, 225 can lead to significant glitches.
Turning now to FIG. 3, illustrated is a graph of glitches associated with prior art DP ladders. As is illustrated, a transition of 0x3Fh to 0x40h leads to significant glitches on an output analog node. In other words, a change from binary equivalent of “63” 0111111 to the binary equivalent of “64”1000000, the LSB bits 0″111111″ converting to 1 “0000000” and the MSB bit “0”111111 converting to a 1 “0000000”, results in a significant glitch. In one example, basically, any change in the MSB string results in a significant glitch. If the MSB string represents the upper 4 bits of the digital code, then a glitch results when any of those upper 4 bits change.
Turning now to FIG. 4, illustrated is a simulation of a quantification of various potential undesired transients that occur for various LSB transitions around an MSB boundary. In the simulation, ether is a 150 mV glitch. Generally, terminology used in the D/A industry to quantify the transient glitch of a D/A converter is to referred to as the “Midscale Glitch”. One reason behind this is that for many D/A architectures, the worst case glitch occurs at midscale and that's what is typically used as a measuring gauge. However, in FIG. 4, all of the transient simulations that had a glitch were overlaid, and the worst one was not the transition at midscale.
Therefore, there is a need in the art to address at least some of the issues associated with conventional DACs, such as digital potentiometers.